# Reference for Concepts :
☞ http://en.wikipedia.org/wiki/Logic_synthesis
☞ http://en.wikipedia.org/wiki/Static_timing_analysis
-> Synthesis and STA(Static Timing Analysis) are related very closely, due to the fact that well-defined constraints in the synthesis will reduce the violations in STA.
( ☞ http://ya-n-ds.tistory.com/1588 : Prime Time )
** DC ( Design Compiler ) : Synthesis
~/syn > dc_sub -short -v DC_Version -Is dc_shell -64 -f ./SCRIPT_DIR/regular/compile.tcl | tee -i ./log/TargetName_LibName.log
~/syn/SCRIPT_DIR > *_define.tcl, *_constraint.tcl // Input files
~/syn/NET_DIR > *.v // Synthesized Netlist
~/syn/SVF_DIR > *.svf // Guidance file for formality
// Netlist and SVF files should be kept for ECO...
~/syn/REPORT_DIR > // Report files to check whether synthesis is done well or not
~/syn/DB_DIR > *.ddc
// a synopsys encrypted form of your design which consists of the netlist(list of components and nets, gate level) information and the constraints
// This file can be read by the tools such as Design compiler, IC compiler and prime time.
<< *_define.tcl >>
set search_path [ concat $search_path $*_dir \ ]
# User define parameters : 0=false, 1=true
set use_clock_gating 1
set use_insert_cg 1
...
set optimize_target { time or area or time_area }
set use_file_list
set use_file_list1
...
# File list
set file_list [ list \
... \
]
set file_list1 [ ... ]
set define_list [ list \
... \
]
set top_design_name "TOP_DESIGN_NAME"
# Caution : The files which do not have module but only task or function shall not to be included in the file list.
# If the parameters in these files are necessary, they shall be included in the RTL which requires the parameters.
<< *_contraint.tcl >>
set period_overhead [expr (0.31 + 0.133)] // [ expr 0.31 + $derate(wst, late, data, $lowest_vt) ]
set margin_ratio [expr ( 1 - $period_overhead ) ]
set CLOCK_FREQ 400
set CLOCK_PREIOD [exp (1000 * $margin_ratio / $CLOCK_FREQ)]
set CLOCK_NAME "xi_clock"
create_clock -name $CLOCK_NAME -period $CLOCK_PREIOD -waveform [ list 0 [expr (0.5 * $CLOCK_PREIOD)] ]
set DIV_NUM 2
set GEN_CLOCK_NAME "xi_clock_gen"
create_generated_clock -name $GEN_CLOCK_NAME -source [get_pins SRC_CLOCK_PIN] -divide_by $DIV_NUM [get pins OUTPUT_CLOCK_PIN]
( -add -master_clock MASTER_CLOCK_NAME -combinational )
set_input_delay_ratio 0.6 // +20% margin
set_output_delay_ratio 0.6
set_ideal_network -no_propagate [fine port "xi_clock"]
set_dont_touch_network [fine port "xi_clock"]
set_dont_touch_network [fine port "xi_resetn"]
set clock_list [find "clock" "*"]
foreach_in_collection clockname $clocklist {
set_ideal_network -no_propagate [find net $clockname]
}
## Output Constraints
set_max_fanout 16.0 $TOP_DESIGN_NAME
set_max_fanout 1.0 [all_inputs]
set_max_transition 1.0 [all_inputs]
