# Reference for Concepts :
☞ http://en.wikipedia.org/wiki/Logic_synthesis
☞ http://en.wikipedia.org/wiki/Static_timing_analysis
-> Synthesis and STA(Static Timing Analysis) are related very closely, due to the fact that well-defined constraints in the synthesis will reduce the violations in STA.
( ☞ http://ya-n-ds.tistory.com/1589 : DC ( Design Compiler ) )
** Flow Concept
< Input >
Netlist Format : Verilog, VHDL, EDIF
Delay Format : SPEF, SPF, SDF
Library Format : DB
< Constraint >
SDC : Create Clocks, I/O delay, ...
< Output >
Timing Analysis Report
** PT w/o script for Debug
~/sta > pt_sub -mem 64000 -lic LICSENCE_NUM -v DC_Version -Is -64 pt_shell -64
cf. DC_Version : 2010.12-SP3-1, 2011.06-SP3-4, etc
pt_shell> restore_session DIR_PATH
// Caution : The session saved with a newer version cannot be read with a older version
< Check Timing >
pt_shell> report_constraint -all_violators // Examine the constraint report
pt_shell> report_constraint -all_violators -verbose
pt_shell> report_timing // What is the worst slack in this design?
pt_shell> report_timing -from startpoint -to endpoint // Look at other violating path from the constraint report
pt_shell> report_analysis_coverage //
pt_shell> report_clock_timing -type skew //
** PT ( Prime Time ) : STA
~/sta > pt_sub -Is -64 -v DC_Version -mem pt_shell -64 -f ./SCRIPT_DIR/SCRIPT_NAME.tcl |& tee ...
// Option : SDC Write, Session Write
~/sta/SCRIPT_DIR > *.tcl // Sript files
~/sta/LOG_DIR > // Log files
<< *.tcl >>
## Environment
source -echo ./SCRIPT_DIR/set_environmet.tcl
## Variable
source -echo ./VARIABLE_DIR/set_pt_variables.tcl
## Design Load
current_design ...
link_design ...
## Operation Condition
source -echo ./SCRIPT_DIR/set_operating_conditions.tcl
## Clock Define
source -echo ./SCRIPT_DIR/set_clock.tcl
# create_clock -name $CLK_NAME -period $CLK_PERIOD -waveform [ list 0 [expr (0.5 * $CLOCK_PERIOD)] ] [get_pins CLK_PIN]
#
# create_generated_clock -name $GEN_CLOCK_NAME -source [get_pins SRC_CLOCK_PIN] -divide_by $DIV_NUM [get pins OUTPUT_CLOCK_PIN]
# ( -add -master_clock MASTER_CLOCK_NAME -combinational )
# POST : set_propagated_clock [all_clocks]
# set_clock_uncertainty -setup * [all_clocks]
## I/O Boundary Constraints Setting
source -echo ./SCRIPT_DIR/set_io_condition.tcl
# set *_in_group [list \
# ... \
# ]
#set_input_delay -max MAX_DELAY_IN_VALUE -clock REF_CLOCK INPUT_LIST
#set_input_delay -min MIN_DELAY_IN_VALUE -clock REF_CLOCK INPUT_LIST
# set *_out_group [list \
# ... \
# ]
#set_output_delay -max MAX_DELAY_OUT_VALUE -clock REF_CLOCK OUTPUT_LIST
#set_output_delay -min MIN_DELAY_OUT_VALUE -clock REF_CLOCK OUTPUT_LIST
## I/O load & Transition & Capacitance
#set all_ins [all_inputs]
#set all_clks [list""]
#set pin_load LOAD_VALUE
#set_load LOAD_VALUE [remove_from_collection $all_ins $all_clks ]
#set_load LOAD_VALUE [all_outputs]
#set_input_transition 1 [ remove_from_collection <base_collection> <items_to_remove> ]
#set_max_capacitance 1 [ remove_from_collection <base_collection> <items_to_remove> ]
## Timing Exception Setting
source -echo ./SCRIPT_DIR/set_timing_exception.tcl
# set_ideal_network -no_propagte [get_pins *]
## Mode Setting
source -echo ./SCRIPT_DIR/set_chip_mode.tcl
# set_case_analysis <0 or 1> [get_pins *]
## Timing Arc Disable Setting
source -echo ./SCRIPT_DIR/set_disable_arc.tcl
# set_disable_timing -from * to * [get_cells *]
## OCV Margin Setting
source -echo ./SRIPT_DIR/set_timing_derate.tcl
